Workshop: 3D Wafer Level Packaging
When? September 13, 2010, 9 a.m. - 6 p.m.
Where? Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin, Germany
Responsible Tutors:
M. Jürgen Wolf (Fraunhofer IZM)
Ehrenfried Zschech (Fraunhofer IZFP-D)
Part 1: 3D Roadmapping
Part 2: 3D Technology Aspects
Part 3: 3D Interconnect Process Control and Quality Engineering
Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing, Dresden, Germany
Ehrenfried Zschech is Division Director at Fraunhofer Institute for Nondestructive Testing in Dresden, which he joint in 2009. His responsibilities include micro- and nanoanalysis as well as R&D in the field of test systems. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. Ehrenfried Zschech gathered experience in industry, during 17 years in several technical and management positions at Airbus and AMD. He has published three books and more than 100 papers in scientific journals in the areas of solid-state physics and materials science. He is honorary professor for nanomaterials at the Brandenburg University of Technology in Cottbus, Germany. In 2009, Ehrenfried Zschech was elected as Vice President of the Federation of European Materials Societies (FEMS).
M. Juergen Wolf, Fraunhofer Institute for Reliability and Microintegration IZM, Berlin, Germany
Since 1994 M. Juergen Wolf is with Fraunhofer IZM, Berlin, where he is currently is in charge of 3D wafer level integration projects and the 300 mm Wafer Level Integration at Fraunhofer IZM and in this context the coordination of IZM’s center “All Silicon System Integration Dresden“ (ASSID). He is a member and European representative in the technical working group Assembly & Packaging of the International Roadmap of Semiconductors (ITRS), the JISSO European Council (JEC), the Jisso International Council (JIC), a board member of EURIPIDES, and a member of IEEE and SMTA. He has authored and co-authored more than 50 papers and reports to microelectronic packaging and he holds a number of patents.
| 9:00 | Welcome | M.J. Wolf, E. Zschech |
| Part 1 9:05-10:30) |
Roadmapping and Application | |
| 09:05-09:30 | Roadmapping - ITRS, Sematech, Industry | Bill Chen |
| 09:30-09:50 | Roadmap Analysis | Jean-Marc Yannou (Yole). |
| 09:50-10:20 | Integrated Solutions for 3D Interconnect | Sesh Ramaswami (Applied Materials) |
| 10:20-10:30 | coffee break | |
| Part 2 (10:30-14:00) |
3D Technology Aspects | |
| 10:30 | 3D wafer level system Integration | M.J. Wolf (IZM) |
| 10:50 | Advanced Electrodeposition Processes for 3D Interconnect | Razalia Beica (Applied Materials) |
| 11:10 | Critical Aspects of Thin Wafer Handling and Bonding for TSV Integration | Thorsten Matthias (EVG) |
| 11:30 | Fine pitch bump connection technology for 3D chip stacking | Masahiro Aoyagi (AIST) |
| 12:00-13:00 | lunch break | |
| 13:00 | Packaging of 3D ICs , Wafer Vs Glass & Si Packages | Rao Tummala (GeogiaTech) |
| 13:20 | Comparative Value Analysis of 3D Packaging Technologies | Chuck Bauer (TechLead Corporation) |
| 13:40-14:00 | Q&A | |
| Part 3 (14:15-17:00) |
3D Interconnect Process Control and Quality Engineering | |
| 14:15-14:45 | 3D Integration: Processes, Materials and Analysis | Ehrenfried Zschech (IZFP-D) Alain Diebold (SUNY) |
| 14:45-15:15 | Fault isolation and microstructure analysis of 3D interconnects | Frank Altmann (IWM) |
| 15:15-16:15 | Optical spectroscopy for bonded wafer inspection: IR, Raman | Alain Diebold (SUNY) |
| 16:15-16:45 | Scanning acoustic microscopy (SAM) for bonded wafer inspection | Bernd Köhler (IZFP-D) |
| 16:45-17.15 | NanoXCT and FIB for failure localization and failure analysis in TSV structures | Peter Krüger (IZFP-D) |
| 17:15-17:45 | Stress-related impact of processing for TSV-based 3D products | Ehrenfried Zschech (IZFP-D) |
| 17:45-18:00 | Q&A | |
