Tuesday, September 14, 2010, 7:30 p.m.
We are very pleased to have a panel of internationally renowned experts who will discuss "Challenges and Opportunities for Chip Embedding Technologies" at the ESTC conference. Where do we stand on the embedding of active ICs? What role will fan-out WLP play in the future? These are only some of the questions the panelists will discuss.

Charles E. Bauer, Ph.D. serves as Senior Managing Director of TechLead Corporation, a technology management company specializing in the electronics packaging, interconnection and assembly industry. Dr. Bauer lectures throughout the world on technology, business and market topics as well as serving on several corporate boards and international corporate, government and educational institution advisory councils. A Senior Member of IEEE, he remains active in the SMTA, JIEP, ASM and IMAPS as well. He currently serves as the International Development Chair for the SMTA. Awards received include Tektronix Technical Innovation Award, Fellow of IMAPS, the International Leadership Award from the SMTA, and SMTA 25th Anniversary Luminary as founder of the Pan Pacific Microelectronics Symposium.

Bernd obtained his PhD in Polymer Chemistry at the University of Mainz, Germany. He started his career in the US as a post-doc at the University of Massachusetts at Amherst, MA, followed by another post-doc at IBM Research in San Jose, CA. Subsequently, he worked for 23 years at IBM in Materials & Process Development of PCBs. There, he held management positions in Manufacturing Engineering, Business Development and Technology Licensing of packaging technologies. In February 2003, he joined ASE US as Director of Substrate Marketing. Since then, he held different positions at ASE Europe and ASE Shanghai. At the end of 2007, Bernd returned to the US to promote ASE Materials Substrates, and recently also Cu Wire Bonding Technology, as Director of World Wide Business Development. Bernd holds more than 50 patents and has authored several book chapters about substrate technologies.

Bernd Römer received his diploma in mechanical engineering and precision engineering from the University of Applied Sciences Giessen/Germany in 1983. He joined the Siemens AG semiconductor group, now Infineon Technologies AG, in 1983. Bernd had various engineering and management positions in the area of semiconductor package / product development, technology & innovation, research & development and production. Currently he is Senior Principal Packaging and System Assembly. He is responsible for the technology innovation for CMOS packaging and system assembly.
Bernd Römer is an active member in different organizations like ITRS TG Assembly & Packaging, JEDEC and JISSO International Council (JIC). He is chair man for the JISSO European Council (JEC). He holds several patents in microelectronic packaging technology.

Dr. Lang studied Electrical Engineering at Humboldt University in Berlin and received two PhD degrees (Wire Bonding of Multilayers and Quality Assurance in Assembly Processes in 1985 and 1989, respectively). In 1993 he joined Fraunhofer IZM, where he held different positions over the years. Since April 1st he has been the (acting) Director of the institute.
Dr. Lang is member of numerous scientific boards and conference committees. Examples are the SEMI Award Committee, the Scientific Advisory Board of EURIPIDES, the Executive Board of VDE-GMM and the scientific Chair of the Conference “Technologies of Printed Circuit Boards” and “SMT/HYBRID/PACKAGING”. He is member of DVS, IEEE, IMAPS and plays an active role in the international packaging community (e.g. German Chapter Chair IEEE-CPMT).

Hannes Stahr heads the implementation of the AT&S group’s R&D branch. Since May 2008 he has been the consortium leader of the FP7 project Hermes. The Hermes consortium consists of 10 European companies and AT&S driving the industrialisation of chip embedding in PWB forward.

Prof. Rao Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF ERC at Georgia Tech, the largest Academic Center in Microsystems pioneering System-On-Package (SOP) vision, since 1994. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage.
Prof. Tummala is a Fellow of IEEE, IMAPS, and the American Ceramic Society, and member of the National Academy of Engineering in USA and in India. He was the President of both IEEE-CPMT and the IMAPS Societies. He has received many industry, academic and professional society awards.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, IMAPS, MEPTEC, and SEMI. She received the “Die Products Industry Achievement Award,” in September 2007. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.