Monday, September 13, 2010, 4 - 6 p.m.
Maritim pro arte Hotel, Berlin

Prof. Keyun Bi is organizing a special "Chinese Session" on the afternoon of September 13. Join us to learn more about China's contribution to developments and applications in packaging technologies.

Complete Session Program with Speaker Bios (.pdf/3MB)

Chair: Prof. Keyun Bi
President of EMPT-CIE, Packaging Branch of CSIA 

Speakers and Presentations:

Prof. Keyun Bi
President of CIE-EMPT, Packaging Branch of CSIA 

The Development of IC Packaging Industry of China
This article first describes the development history and the status quo of the electronic packaging industrial chain of China, providing plenty of statistic data. This article then, explained the counter-measures taken by Chinese government for this industry to battle with the impact of world financial crisis. After the explanation of the status quo, the author provides a questionnaire by which he wants to exchange ideas with the audience.

 

Wade Lam
Chairman of Grand Tech Group Ltd

Grand Tech Group,Your Automation Solution And Innovation Partner
A general outlook of the IC assembly market in China is provided in this article. The author will introduce the manufacturing capability and automation equipment developed by Grand. The important purpose is to introduce the advantages of one-stop service for equipment manufacturer in IC assembly equipment market for Chinese local customers and to find opportunities of cooperation with European countries.

 Prof. Zhiyue Wang
Deputy Director General of the 45th Research Institute of Chinese Electronic Technology Group Company (CETC)

The Status Quo and Developing Trend of Chinese Packaging Equipment Industry for IC
This paper described the current status of IC packaging industry and IC packaging equipment in China, with emphasis on the analysis for market situation of packaging equipment. The paper introduced vigorous supports to packaging equipments and processes from relevant Chinese government agencies, with significant achievements in the area. Constructive opinions were given on the development trends of Chinese IC packaging equipment in recent years. Finally brief introduction was given on the R&D achievements and recent progress of The 45th Institute of China Electronics Technology Group Corporation, one of the famous major packaging equipment manufacturers in China.

Dr. Weiping Li
Corporate VP, New Technologies and US & Europe Markets, Jiangsu Changjiang Electronics Technology Co., Ltd (JCET)

MIS Package – The New Generation Packaging Technology for High-Performance Applications
It has been more than 10 years since the first introduction of QFN packaging technology. The huge success and wide proliferation of QFN is a testimony of the rapid development and dominance of mobile and consumer electronics . While QFN was able to meet many of the new demands and challenges, it has been slow for the development and adoption of high-pin count QFN packages. As a result, ICs of 100-400 pin counts are still mostly packaged in QFP, CSP and BGA format, each with advantages and disadvantages.
This presentation introduces and describes an innovative new generation of QFN packaging technology. The patented Molded Interconnection System (MIS) leadframe technology has the unprecedential fan-in capability for leadframes with routing capabilities and densities matching those of 2-layer laminate substrates, yet at much lower costs. With multi-row I/O designs, MIS packages can easily support IC’s with I/O counts from 100 through 400, far exceeding the current QFN packages. MIS technology is also capable of first level interconnections of wirebond, flip chip and POP (package on package).  Furthermore, MIS packages can be designed with superior thermal properties for high-power devices. After nine months intensive product development and qualification, JCET is working with several key IC manufacturers and packaging subcons in the pre-production of MIS technology. It is predicted that the low-cost, small size and high electrical and thermal performance of MIS would enable a new generation of packaging technology since the introduction of QFN.

Dr. Hao Tang
Director of Technology, Nantong Fujitsu Microelectronics Co., Ltd

Advanced Semiconductor Packaging Solutions from QFN to 3D, WLP and more
This presentation reviews Nantong Fujitsu’s advanced packaging technology development activities with some examples.  By feature of structure, we refer the advanced package mainly to:    

• lead frame based QFN/DFN package;
• substrate based stack die CSP, flip chip BGA , system in package and package on package;
• wafer level package (WLP).

While researching and developing high performance package construction and optimizing manufacture process, we have put a focus on low cost and high quality in production as well.   With increased level of system integration, chip-package-board co-design approach becomes essential for us to further optimize system performance and reduce product cost. 

Dr. Daquan Yu,
Professor at Institute of Microelectronics, Chinese Academy of Sciences

Key Technologies Developed for System in Package (SiP) at Institute of Microelectronics of Chinese Academy of Sciences (IME-CAS)
System in Package (SiP) is a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices. Numerous concepts for 3D SiP packaging are now emerging driven largely by the demands of portable consumer products. In IME-CAS, packaging research center (PRC), several key technologies, e. g., flip chip, optical connection, through silicon via (TSV), embedded passive, wafer level bumping are under developing. In this presentation, the progress of above studies is introduced and the challenges are also discussed. In addition, the brief introduction of IME-CAS and PRC is also presented.

With continued demand for semiconductor component to be higher in performance, smaller in size, advanced packaging technology has been developed and progressed rapidly in past decade.   With more silicon value moving to the package, it opens up a possible supply chain value change.  IDM, wafer foundries, packaging house, and material supplier all poised to take on more values in this new era.